Reducing Dynamic Energy of Variable Level Cache

Reducing Cache Energy Through Dual Voltage Supply

Due to a large capacitance and enormous access rate, caches dissipate about a third of the total energy consumed by today’s processors. In this paper we present a new architectural technique to reduce energy consumption in caches. Unlike previous approaches, which have focused on lowering cache capacitance and the number of accesses, our method exploits a new freedom in cache design, namely the...

Reducing Instruction Cache Energy Using Gated

The power dissipated by the level-1 Instruction cache is often a considerable part of the total power dissipated by the entire microprocessor. In this thesis, we focuses on reducing the power consumption of the I-cache by using an in-cache instruction compression technique that uses gated wordlines to reduce the number of bitline swings. First, we develop a cache power consumption model to esti...

Dynamic cache reconfiguration based techniques for improving cache energy efficiency

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii CHAPTER

Let Caches Decay : Reducing Leakage Energy via Exploitation of Cache

Reducing Energy Consumption using a Non-Volatile storage cache

We can outperform the most powerful disk spin-down algorithm available by using a small non-volatile storage write-only cache to temporarily store hard disk write requests while a disk is spun-down. In our experiments, we use a USB thumb drive device as our non-volatile storage cache. By redirecting writes to a flash memory while a disk is spun-down we avoid costly hard disk cycle start-stop op...